Texas

TEXAS INSTRUMENTS: TECHNICAL TEST
Date: 20th December 2003Venue: TAJ LANDS END, BANDRA-WEST, MUMBAINote: Out of 100 candidates only 7 were short-listed)
1. For a CMOS inverter, the transition slope of Vout vs Vin DC characteristics can be increased (steeper transition) by:
a. Increasing W/L of PMOS transistor b. Increasing W/L of NMOS transistor c. Increasing W/L of both transistors by the same factord. Decreasing W/L of both transistor by the same factor
2. Minimum number of 2-input NAND gates that will be required to implement the function: Y = AB + CD + EF isa. 4b. 5c. 6d. 7
3. Consider a two-level memory hierarchy system M1 & M2. M1 is accessed first and on miss M2 is accessed. The access of M1 is 2 nanoseconds and the miss penalty (the time to get the data from M2 in case of a miss) is 100 nanoseconds. The probability that a valid data is found in M1 is 0.97. The average memory access time is:a. 4.94 nanosecondsb. 3.06 nanosecondsc. 5.00 nanosecondsd. 5.06 nanoseconds
4. Interrupt latency is the time elapsed between:a. Occurrence of an interrupt and its detection by the CPUb. Assertion of an interrupt and the start of the associated ISRc. Assertion of an interrupt and the completion of the associated ISRd. Start and completion of associated ISR
5. Which of the following is true for the function (A.B + A’.C + B.C)a. This function can glitch and can be further reducedb. This function can neither glitch nor can be further reducedc. This function can glitch and cannot be further reducedd. This function cannot glitch but can be further reduced

6. For the two flip-flop configuration below, what is the relationship of the output at B to the clock frequency?a. Output frequency is 1/4th the clock frequency, with 50% duty cycleb. Output frequency is 1/3rd the clock frequency, with 50% duty cyclec. Output frequency is 1/4th the clock frequency, with 25% duty cycled. Output frequency is equal to the clock frequency



A B




7. The voltage on Node B is:a. 0b. 10c. –10d. –5

+ + 10V 20V_ _
GND B



8. A CPU supports 250 instructions. Each instruction op-code has these fields:• The instruction type (one among 250)• A conditional register specification• 3 register operands• Addressing mode specification for both source operands
The CPU has 16 registers and supports 5 addressing modes. What is the instruction op-code length in bits?a. 32b. 24c. 30d. 36
9. In the iterative network shown, the output Yn of any stage N is 1 if the total number of 1s at the inputs starting from the first stage to the Nth stage is odd. (Each identical box in the iterative network has two inputs and two outputs). The optimal logic structure for the box consists of:a. One AND gate and one NOR gateb. One NOR gate and one NAND gatec. Two XNOR gatesd. One XOR gate
I 1 I 2 I n I n +1 I n + 2

0

Y1 Y2 Yn Yn+1 Yn+2
10. Consider a circuit with N logic nets. If each net can be stuck-at either values 0 and 1, in how many ways can the circuit be faulty such that only one net in it can be faulty, and such that up-to all nets in it can be faulty?a. 2 and 2Nb. N and 2^Nc. 2N and 3^N-1d. 2N and 3N




11. In the circuit shown, all the flip-flops are identical. If the set-up time is 2 ns, clock->Q delay is 3 ns and hold time is 1 ns, what is the maximum frequency of operation for the circuit?
D1 Q1 D2 Q2 D3 Q3


CLOCK SIGNAL

a. 200 MHzb. 333 MHzc. 250 MHzd. None of the above
12. Which of the following statements is/are true?I. Combinational circuits may have feedback, sequential circuits do not.II. Combinational circuits have a ‘memory-less’ property, sequential circuits do not.III. Both combinational and sequential circuits must be controlled by an external clock.
a. I onlyb. II and III onlyc. I and II onlyd. II only
13. Consider an alternate binary number representation scheme, wherein the number of ones M, in a word of N bits, is always the same. This scheme is called the M-out-of-N coding scheme. If M=N/2, and N=8, what is the efficiency of this coding scheme as against the regular binary number representation scheme? (As a hint, consider that the number of unique words represent able in the latter representation with N bits is 2^N. Hence the efficiency is 100%)a. Close to 30%b. Close to 50%c. Close to 70%d. Close to 100%
14. A CPU supports 4 interrupts- I1, I2, I3 and I4. It supports priority of interrupts. Nested interrupts are allowed if later interrupt is higher priority than previous one. During a certain period of time, we observe the following sequence of entry into and exit from the interrupt service routine:I1-start---I2-start---I2-end---I4-start---I3-start---I3-end---I4-end---I1-endFrom this sequence, what can we infer about the interrupt routines?a. I3 > I4 > I2 > I1b. I4 > I3 > I2 > I1c. I2 > I1; I3 > I4 > I1d. I2 > I1, I3 > I4 > I2 > I1
15. I decide to build myself a small electric kettle to boil my cup of tea. I need 200 ml of water for my cup of tea. Assuming that typical tap water temperature is 25 C and I want the water boiling in exactly one minute, then what is the wattage required for the heating element?[Assume: Boiling point of water is 100 C, 1 Calorie (heat required to change 1 gm of water by 1 C)= 4 joules, 1 ml of water weighs 1 gm.]a. Data given is insufficientb. 800 Wc. 300 Wd. 1000 We. 250 W
16. The athletics team from REC Trichy is traveling by train. The train slows down, (but does not halt) at a small wayside station that has a 100 mts long platform. The sprinter (who can run 100 mts in 10 sec) decides to jump down and get a newspaper and some idlis. He jumps out just as his compartment enters the platform and spends 5 secs buying his newspaper that is at the point where he jumped out. He then sprints along the platform to buy idlis that is another 50 mts. He spends another 5 secs buying the idlis. He is now just 50 mts from the other end of the platform where the train is moving out. He begins running in the direction of the train and the only other open door in his train is located 50 mts behind the door from where he jumped. At what(uniform) speed should the train be traveled if he just misses jumping into the open door at the very edge of the platform?Make the following assumptions• He always runs at his peak speed uniformly• The train travels at uniform speed• He does not wait (other than for the idlis & newspaper) or run baclwards
a. Data given is insufficientb. 4 m/sc. 5 m/sd. 7.5 m/se. 10 m/s
17. State which of the following gate combinations does not form a universal logic set:a. 2-input AND + 2-input ORb. 2-to-1 multiplexerc. 2-input XOR + inverterd. 3-input NAND

18.For the circuit shown below, what should the function F be, so that it produces an output of the same frequency (function F1), and an output of double the frequency (function F2).



IN OUT INVERTER

a. F1= NOR gate and F2= OR gateb. F1=NAND gate and F2= AND gatec. F1=AND gate and F2=XOR gated. None of the above






19. The FSM (finite state machine) below starts in state Sa, which is the reset state, and detects a particular sequence of inputs leading it to state Sc. FSMs have a few characteristics. An autonomous FSM has no inputs. For a Moore FSM, the output depends on the present state alone. For a Mealy FSM, the output depends on the present state as well as the inputs. Which of the statements best describes the FSM below?
a. It has two states and is autonomousb. The information available is insufficientc. It is a Mealy machine with three statesd. It is a Moor machine with three states



0 1 0 1 0







20. In the circuit given below, the switch is opened at time t=0. Voltage across the capacitor at t=infinity is:a. 2Vb. 3Vc. 5Vd. 7V


+ +
__











21. What is the functionality represented by the following circuit?a. y= ! (b+ac)b. y= ! (a+bc)c. y= ! (a(b+c))d. y= ! (a+b+c)Vcc

A



B Y



C


22. The value (0xdeadbeef) needs to stored at address 0x400. Which of the below ways will the memory look like in a big endian machine:
0x403 0x402 0x401 0x400a. be ef de adb. ef be ad dec. fe eb da edd. ed da eb fe
23. In a given CPU-memory sub-system, all accesses to the memory take two cycles. Accesses to memories in two consecutive cycles can therefore result in incorrect data transfer. Which of the following access mechanisms guarantees correct data transfer?a. A read operation followed by a write operation in the next cycle.b. A write operation followed by a read operation in the next cycle.c. A NOP between every successive reads & writesd. None of the above
24. An architecture saves 4 control registers automatically on function entry (and restores them on function return). Save of each registers costs 1 cycle (so does restore). How many cycles are spent in these tasks (save and restore) while running the following un-optimized code with n=5:
Void fib(int n){ if((n==0) (n==1)) return 1; return(fib(n-1) + fib(n-2));}a. 120b. 80c. 125d. 128
25. The maximum number of unique Boolean functions F(A,B), realizable for a two input (A,B) and single output (Z) circuit is:
a. 2b. 6c. 8d. None of the above



TECHNICAL TEST: -------------------------
1)3 flipflops are connected so that after 0 to 5 count occured next number is zero. So what is the counter? Ans: mod 6 counter 2)simplication of some boolean expression which is simple. Boolean Expression is A+A'B. Ans:A+B 3)Given inorder sequence and preorder sequence and asked to find out postorder sequence. 4)Some question on value of a static variable. 5) Given an interger in binary form,find the number of ones in that number without counting each bit.(This questin is not multiple choice question. This question carries more marks. So please take care for this question.) 6) 1-way set associative memory is called----- a)direct b)something c)1-way set associative 4)something Ans: c 7)Fastest IPC mechanism is a)shared memory b)pipes c)named pipes d)semaphores Ans:c 8)Some page references are given. You are asked to implement it with Least Frequently Used algorithm.
9)Some diagram is given. Iam describinmg the diagram. A 2*1 MUX is given. The inputs are A,B. Output is C. C and A are tied together. What is the diagram.?
Ans:Latch.
**************************************************************
This paper is for Electrical & Electronics students. There is separate test for computer Science Students. There are 20 questions.
1)Some circuit is given. Iam describing the circuit. A resistor R & a capacitor C are connected in parallel. To this circuit another circuit which is having a capacitor of capacity 2C & an impedence Z, is connected in series. You are asked to find out the value of Z? Note that 2C & Z are connected in series. a)Z=2C b)Z=2L c)Z=L/2 d)Z=2R 2)Some circuit which consist of only resistors R is given. This is a repetative circuit. U have to find the effctive resistance of the entire circuit. A)Rin=R B)Rin=(5+sqrt(3))/7 C)Rin=(19+sqrt(3))/8 D)None. 3)Two wave forms are given. You are asked to write the cirsuit to get B(second wave form) from A(first wave form). 4)#define SUM(a,b) a+b
main() { a=2; b=3; x=SUM(a,b)*2; printf("x=%d\n",x); } Ans:8.
5)number(int i){number++;printf("%d\n",number);}
main(){static int i=0;number(i);}Ans: I don't know.
6)Some circuit is given. I can't describe the circuit. There are 3 resistors,3 capacitors & one inverter.. The question is What is the value of the frequency such that the circuit oscillates. A)f=RC B)f=sqrt(3)/(Pi*R*C) C)f=1/(Pi*R*C) D)something Ans:I don't know the answer.
7)Question on flipflop. So gothrough all flipflops.
8)There are 5 questions on Nmos & Pmos circuits. **************************************************************This Paper is for Computer Science Students. THis paper isvery easy. You can definitely do it in one hour.**************************************************************
(1) The fastest memory is(i) DRAM, (ii) ROM, (iii) SRAM, (iv) Main memoryAns : SRAM
(2) Programing exceptions are (i) Asynchronous, (ii) Synchronous, (iii) NoneAns : Asynchronous
(3) DSP which architecture is used(i) MIMD, (ii) SIMD, (iii) Nueman, (iv) Harvard ArchitectureAns : Harvard Architecture
(4) C prog. for searching for an element in linked list
(5) main(){ unsigned char i; int sum;
for(i=0; i<300; i++) sum+ = i; printf("\nSum = %d\n", sum);}
Ans : infinite loop
(6) void fn(int *p) { static int val = 100; p = &val; }
main(){ int i=10; printf("i=%d\n", i); fn(&i); printf("i=%d\n", i);}
Ans : i=10 i=10
(7) int a[10[15]; char b[10[15]; (a) location g a[3][4], if base location g a[0][0] is ox1000 (b) location g b[3][4], if base location g b[0][0] is ox2000 int taken 32 bits and char taken 8 bits.
Ans : (a) ox10C4 (b) ox2031
(8) Implement OR gate function with 2*1 MUX
Ans : A ___________ --------2*1 MUX B --------o/p -------- ----------- _______C
B=C
(9) Implement 4*1 MUX with 2*1 MUXES
(10) Swapping without using a temporary variables. (2 methods)
(i) x = x+y; y = x-y; x = x-y;
(ii) x = x^y; y = x^y; x = x^y;
(11) Count no of 1's in a word without using bit by bit. (This question carries more marks. It is not a multiple choice question.)
(12) Code 1 : for(i=0; i<1000; i++) for(j=0; j<100; j++) x = y;
Code 2 : for(i=0; i<100; i++) for(j=0; j<1000; j++) x = y;
Which code will execute faster(i) Code 1 and Code 2 are of same speed,(ii) Code 1,(iii) Code 2,(iv) None.
Ans : Code 2
(13) main() { int a[10] = {1, 2, 3, ...., 10}, i, x=10, temp;
for(i=0; iAns : (iii)
(14) An array is stored in row major order. The memory capacity is 30 MB. And in unix system demand paging is used. Which one will give more page faults?
#define V_L_I 10000 int i, j, array[V_L_I][V_L_I];
Code 1 : array[i][j] = 1;
Code 1 : for(j=0; jAns : Code 2
(15) In C which parameter passing technique is used?(i) call by value,(ii) call by reference,(iii) both
Ans : call by value
(16) A circuit is given with 2 exclusive OR gates whose boolean expression will be y = '(AB) + AB (' indicates bar)
(17) main() { int i = 1; fork(); fork(); printf("\ni = %d\n", i+1); }
Ans : 4 printfs will occur and i = 2
(18) Compute the complexity of Binary search.Ans : O(lg n) ( Answer in detail. This is not a multiple choice question. It carries more marks.)
(19) Write expression for the tree graph :Ans : ((a-b) + c*d)/x
(20) # define MAX(a, b) a>b ? a:b main() { int m, n; m = 3 + MAX(2, 3); n = 2 * MAX(3, 2); printf("m = %d, n = %d\n", m, n) } Ans : m=2, n=3